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| TM ACS03MS Radiation Hardened Quad 2-Input NAND Gate with Open Drain Pinouts 14 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C TOP VIEW A1 1 14 VCC 13 B4 12 A4 11 Y4 10 B3 9 A3 8 Y3 January 1996 itle CS0 S) bt adian rded ad nput ND te th en ain) utho ) eyrds terrpoion, minctor, dian rded, , d rd, L, tel, Features * Devices QML Qualified in Accordance with MIL-PRF-38535 * Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96703 and Intersil's QM Plan * 1.25 Micron Radiation Hardened SOS CMOS * Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si) * Single Event Upset (SEU) Immunity: <1 x 10 -10 Errors/Bit/Day (Typ) * SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg * Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse * Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse * Latch-Up Free Under Any Conditions * Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC * Significant Power Reduction Compared to ALSTTL Logic * DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V * Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min * Input Current 1A at VOL, VOH * Fast Propagation Delay . . . . . . . . . . . . . . . . 15ns (Max), 10ns (Typ) B1 2 Y1 3 A2 4 B2 5 Y2 6 GND 7 14 PIN CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C TOP VIEW A1 B1 Y1 A2 B2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC B4 A4 Y4 B3 A3 Y3 Description The Intersil ACS03MS is a Radiation Hardened quad 2-input NAND gate with open drain outputs. The open drain output can drive resistive loads from a separate supply voltage. The ACS03MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of a radiation hardened, high-speed, CMOS/SOS Logic Family. The ACS03MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a Ceramic Dual-In-Line Package (D suffix). Ordering Information PART NUMBER 5962F9670301VCC 5962F9670301VXC ACS03D/Sample ACS03K/Sample ACS03HMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC 25oC 25oC 25oC SCREENING LEVEL MIL-PRF-38535 Class V MIL-PRF-38535 Class V Sample Sample Die PACKAGE 14 Lead SBDIP 14 Lead Ceramic Flatpack 14 Lead SBDIP 14 Lead Ceramic Flatpack Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 Spec Number File Number 1 518779 3064.1 ACS03MS Functional Diagram An Yn Bn TRUTH TABLE INPUTS An L L H H NOTES: 1. L = Low, H = High, Z = High Impedance 2. Without Pull-up Resistor 3. With Pull-up Resistor Bn L H L H OUTPUT Yn Z (Note 2), H (Note 3) Z (Note 2), H (Note 3) Z (Note 2), H (Note 3) L 2 Spec Number 518779 ACS03MS Die Characteristics DIE DIMENSIONS: 68 mils x 79 mils 1730mm x 2010mm METALLIZATION: Type: AlSi Metal 1 Thickness: 7.125kA 1.125kA Metal 2 Thickness: 9kA 1kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: <2.0 x 105A/cm 2 BOND PAD SIZE: 110m x 110m 4.3 mils x 4.3 mils Metallization Mask Layout ACS03MS B1 (2) A1 (1) VCC (14) B4 (13) Y1 (3) (12) A4 A2 (4) (11) Y4 B2 (5) (10) B3 Y2 (6) (9) A3 (7) GND (8) Y3 Spec Number 3 518779 |
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